Character:
●DDR3 UDIMM 1333Mhz/1600Mhz
●VDD = VDDQ = 1.5V (1.48V to 1.57V)
●VDDSPD = 3.0V to 3.6V
●Fully differential clock inputs (CK, CK)
●Differential Data Strobe (DQS, DQS)
●On-die DLL aligns DQ, DQS, and DQS transitions with CK transitions
●DM masks data on both rising and falling edges of Data Strobe
●All address and control inputs except data, Data Strobe, and Data Mask are latched on the rising edge of the clock
●Supports programmable CAS Latency of 5, 6, 7, 8, 9, 10, 11, 13
●Supports programmable Additive Latency of 0, CL-1, and CL-2
●Programmable CAS Write Latency (CWL) = 5, 6, 7, 8, 9
●Programmable Burst Length of 4/8 with half-byte sequence and interleaved mode
●Instantaneous Burst Length (BL) switching
●Average refresh period: 7.8 μs from 0°C to 85°C
●JEDEC standard 78-ball FBGA (x8)
●Driver strength selectable via EMRS
●Supports dynamic chip termination
●Supports asynchronous RESET pin
●Supports ZQ calibration
●Supports TDQS (Terminated Data Strobe) (x8 only)